1. Field of the Invention
The present invention relates to a compound semiconductor device and, more particularly to a structure of a via hole (through-hole) in said semiconductor device and a method and an etchant used for manufacturing the via hold.
2. Discription of the Related Art
Where an IC (integrated Circuit) is to be designed to be used at a frequency higher than quasi-microwave band, since the behavior of electrons as waves cannot be disregarded, the IC must be designed as a distributed constant line. As this distributed constant line, a microstrip circuit line is widely used.
Where a microstrip line is used, as schematically shown in FIG. 17, a via hole 104 must be formed in order to electrically connect an electrode pad 102 on the front surface of a GaAs substrate 101 to a ground conductor, which is metal, on the back surface thereof, and a strip conductor 105 is formed on the front surface of the GaAs substrate 101.
FIG. 18 shows a sectional view when a semiconductor chip (hereinafter referred to as "IC substrate") is die-bonded to a package substrate 106 using AuSn solder 107. As shown in FIG. 18, in order to prevent "solder upheaval or permeance", a barrier metal 108 of e.g. Ni was formed in only a region constituting the via hole 104a on the surface of the conductive Au film 104b.
Further, as shown in FIG. 18, the region occupied by the via hole 104a corresponds to a region whose diameter is twice or more as large as the thickness of the GaAs substrate 101.
The semiconductor device having the same structure as the via hole structure is disclosed in JP-A-2-162735.
Referring now to FIG. 19, an explanation will be given of a method of forming a via hole described in the reference.
First, as shown in FIG. 19(a), an electrode pad 102 is patterned on the front surface of a GaAs substrate 101. As shown in FIG. 19(b), on the back surface of the GaAs substrate 101, an etching mask 109a having an opening pattern is patterned at the area corresponding to the electrode pad 102. Further, as shown in FIG. 19(c), the back surface of the GaAs substrate 101 is subjected to wet etching to form an opening 109. In this case, the diameter of the opening 109 at the back surface of the GaAs substrate 101 is twice or so as large as the thickness of the GaAs substrate 101. As shown in FIG. 19(d), the etching mask 109a is removed.
As shown in FIG. 19(e), a conductive Au film 104b is plated onto the entire back surface of the GaAs substrate 101.
Thereafter, as shown in FIG. 19(f), a resist pattern 110 is formed at an area except the region constituting the via hole 104a on the back surface of the GaAs substrate 101.
The resist pattern 110 has an opening pattern at the area corresponding to the via hole 104a.
As shown in FIG. 19(g), the GaAs substrate 101 is subjected to electrolytic or non-electrolytic Ni plating to form a barrier metal 108 of Ni on the surface of the via hole 104a.
As shown in FIG. 19(h), the resist pattern 110 is etched away to complete an IC substrate.
The back surface of the IC substrate shown in FIG. 19(h) is bonded to the front surface of the package substrate 106 to provide a semiconductor device having a sectional structure as shown in FIG. 18.
However, the semiconductor device thus manufactured has the following defects. In the via hole 104 included in the semiconductor device shown in FIG. 18 (via hole 104a in FIG. 19) is opened by wet etching it reaches the front surface of the GaAs substrate 101 from the back surface thereof.
However, when the via hole is opened by the wet etching as described above, the diameter of the opening 109 formed on the back surface of the GaAs substrate 101 was twice or more as large as the thickness of the GaAs substrate 101. With development of miniaturization of the semiconductor device, reduction of the via hole 104a is a critical problem to facilitate device miniaturization.
In order to solve this problem, one of the inventors of the present invention has already accomplished a semiconductor device in which an opening with a high aspect ratio is made by RIE (Reactive Ion Etching) and an via hole is formed in the opening.
FIG. 20(a) shows a sectional structure of the via hole disclosed in JP-A-7-193214.
In FIG. 20(a), reference numeral 111 denotes an underlying wiring 111 applied to the back surface of the GaAs substrate 101; 112 denotes a film stacked on the front surface of the GaAs substrate 101 which is an insulating film serving as an etching mask when the opening 109 for making a via hole is formed; 113 denotes a sputter layer having a two-layer structure of a layer of any material of Ti, Cr and Ni, and Au, which is stacked on the internal wall of the opening 109; 114 denotes an non-electrolytic Ni plating layer stacked in the opening 109 where the sputter layer 113 is stacked; 115 denotes an Au plating layer stacked on the surface of the non-electrolytic plating layer 114; and 116 denotes a power supply layer consisting of the sputter layer 113, non-electrolytic Ni plating 114 and Au plating layer 115.
In the semiconductor device described above, because the internal wall of the opening does not become flat when the sputter layer 113 serving as a catalyst for film deposition by plating, the non-electrolytic Ni plating layer 114 is further deposited on the internal wall and bottom of the opening 109a constituting the via hole 104a within the GaAs substrate 101 so that their surface becomes flat. Thus, the Au plating layer 115 which is a main part of the power supply layer 116 could be formed to have a uniform thickness along the front surface of the GaAs substrate 1 and the shape of the internal wall of the opening constituting the via hole 104a.
The above reference describes that the via hole 10a shown in FIG. 20(a) is made as follows. The insulating film 112 is patterned as an etching mask pattern on the surface of the GaAs substrate 101. Using it as the etching mask, the opening 109 (not penetrating through the GaAs substrate 101) having a high aspect ratio is formed. After the power supply layer 116 is formed within the opening, the back surface of the substrate 101 is etched back until part of the power supply layer 116 is exposed. Finally, the underlying wiring 111 is formed on the back surface of the GaAs substrate 101.
By forming the via hole 104a within the opening with a high aspect ratio having a structure as shown in FIG. 20(a), it can have an occupying area that is a factor of a few when the opening was made by wet etching.
The present invention has been accomplished in order to solve the above problem, and intends to provide a semiconductor device having a stable structure which has a via hole with a small occupying area, does not generate "solder upheaval" phenomenon and makes no crack, a method of manufacturing it and an etchant suitable for the method.